module set_parameter_register #
(
    parameter               WIDTH = 128
)
(
    input   wire                csi_clk,
    input   wire                rsi_reset_n,

    /*port*/
    input   wire [03:00]        avs_address,
    input   wire                avs_write,
    input   wire [31:00]        avs_writedata,

    output  reg  [WIDTH-1:00]   user_parameter
);

reg     [WIDTH-1:00]         user_parameter_r;

always @ (*)
begin
    if(avs_write)
    begin
        case (avs_address)
            0: user_parameter_r[031:000] = avs_writedata;
            1: user_parameter_r[063:032] = avs_writedata;
            2: user_parameter_r[095:064] = avs_writedata;
            3: user_parameter_r[127:096] = avs_writedata;
            default: ;
        endcase
    end
end

always @ (posedge csi_clk or negedge rsi_reset_n)
begin
    if(~rsi_reset_n)
        user_parameter <= 0;
    else
        user_parameter <= user_parameter_r;
end
endmodule
